1. Field of the Invention
The present invention relates to an information processing apparatus including a WideIO memory device stacked on a SOC (System On a Chip) die including a CPU, a method of controlling the same, and storage medium.
2. Description of the Related Art
In an information processing apparatus including a CPU such as a microprocessor, a DRAM is often used to save data for executing an OS and various applications, and to temporarily save data for executing image processing. This DRAM is used as it is connected to a CPU, SOC (System on a Chip), or the like. Recently, the memory bandwidth of the DRAM is increasing as multifunctional high-performance image processing apparatuses have been developed. To increase the memory bandwidth, the clock frequency of memory access is raised in the standards such as DDR3 (Double-Date-Rate3) or DDR4. In addition, the memory bandwidth is secured by using a plurality of DRAM channels connected to a CPU or ASIC (Application Specific Integrated Circuit). However, raising the clock frequency or using a plurality of memory channels poses the new problem that the power consumption increases.
A next generation DRAM standard is presently attracting attention. WideIO is formed by stacking a DRAM chip on a SOC die by using a 3D stacking technique using a TSV (Through Silicon Via). WideIO has the features that a high bandwidth of a maximum of 12.8 (GB/sec) or more is obtained with a large data width of 512 bits, and the power consumption is low because the access frequency is lowered. Also, the use of the TSV can make the package thinner and smaller than that of conventional PoP (Package on Package). In addition, as a measure to heat generated because the memory is stacked in the SOC package, a temperature sensor for sensing the temperature of the memory is incorporated, and the self-refresh rate is changed in accordance with the sensed temperature. Furthermore, the 512-bit data width is divided into four 128-bit channels, and these channels can be controlled independently of each other. For example, it is possible to set channels 1 and 2 in a self-refresh state, and use channels 3 and 4 in normal memory access. The basic structure and basic access method of WideIO are described in U.S. Patent Application Publication No. 2012/0018885 A1.
The multilayered structure of WideIO is susceptible to heat. For example, when a specific region of the SOC die and the WideIO DRAM positioned in an upper layer of this specific region are simultaneously activated, the temperature of the activated portions locally rises. Therefore, it is necessary to shorten the refresh interval of the DRAM. In addition, the power consumption increases due to the influence of a semiconductor leakage current that exponentially increases with respect to the temperature. Since the temperature locally rises, the refresh frequency of the whole DRAM must be increased for the partial region of the DRAM, so the access performance of the DRAM decreases. When the access performance of the DRAM thus decreases, the performance of a system including this SOC package decreases, and this decreases the product performance.
To improve the system performance, it is particularly necessary to take account of the performance of a module as a bottleneck. This is so because the decrease in performance of a bottleneck module directly leads to the decrease in system performance. Especially in the WideIO DRAM, the above-described heat influence is a big problem. That is, the amount of access of a bottleneck module to the DRAM is large, and the large amount of access from this module raises the temperature of the WideIO DRAM. This temperature rise makes it necessary to increase the DRAM refresh frequency described above, thereby decreasing the DRAM access performance. This vicious cycle decreases the performance of the bottleneck module, and the system performance decreases accordingly.